In the microelectronics industry semiconductor product reliability has become increasingly competitive and more difficult to achieve. Recent experience has indicated that growing hardware complexity is creating added latent defects which present new, formidable challenges to microelectronics. Reliability failures generally occur within device cells by defect leakage, charge accumulation, electromigration and dielectric breakdown.
The reliability of electronic components for computers is increasingly more important as electronic devices become more sophisticated in response to the demands of computer users for increased performance. Increased hardware complexity creates more latent reliability exposures than previously experienced.
The commonly used techniques for exposing electronic devices to reliability stress tests and burn-in are to apply to external terminals of the devices forced currents or forced voltages usually with the electronic device held at an elevated temperature. Examples of external terminals are chip pads, substrate pads, pins or other outputs on modules containing chips mounted onto substrates. These techniques are labor intensive, therefore, they are high cost methods which substantially increase the cost of the manufactured electronic devices.
Commonly used stress tests and burn in of electronic devices require special fixtures for holding the electronic device under test and to provide the forced currents and voltages. In the case of semiconductor chips, each chip is typically mounted onto such a holder, stress tested, burned in, and thereafter the device must be removed from the holder for mounting onto a substrate to be used in a fabricated product. When a semiconductor chip packaging substrate, such a ceramic substrate, a polymer substrate, a printed circuit board, a tape automated bonding lead Frame and the like, are stress tested and burned-in, similar special holding structures must be used.
Burn-in and thermal cycling are stress application methods of causing reliability failures to manifest themselves in electronic devices in the factory prior to customer shipment through separate and distinct acceleration techniques.
During burn-in, defects are accelerated primarily by electrical stimuli (current and voltage), and secondarily by constant high temperature. The acceleration due to constant temperature --A(t)-- is defined by the Arrhenious Model: EQU (h/k)(1/T.sub.u -1/T.sub.s) EQU A(t)=e
where h=Activation Energy
k=Boltzman's Constant (8.625.times.10.sup.-5 electrons/K(degrees) PA1 T.sub.W is the use temperature PA1 T.sub.S is the stress temperature PA1 .gamma. is the fail distribution parameter which is derived through voltage acceleration modeling PA1 V.sub.S is the stress voltage
The Acceleration due to electrical stimulus (voltage) is defined by: EQU .gamma.(V.sub.s -V.sub.n) EQU A(v)=e
V.sub.n is the nominal operating voltage
Defects accelerated by burn-in typically are detected as shorts or opens.
During thermal cycling, defects are accelerated by temperature excursions causing failures to show themselves due to temperature coefficient of expansion (TCE) mismatches between the various materials used in device fabrication (such as between silicon and aluminum) and can be considered fatigue fails (or fail by a fatigue mechanism). This distinctly unique stress condition allows detection of distinctly unique defects that are not detectable via burn-in techniques.
Thermal cycle actuated fails typically are opens. The most prevalent example is `seams`. Seams are reduction in the thickness of metal lines due primarily to an overly steep via causing a non-uniform deposition of metal at the steepest point. At the apex, the metal is very thin but conductive, however, the TCE mismatch during thermal cycling causes this very thin line to crack and become open. Seams cannot be accelerated by burn-in, since by definition, burn-in is done at uniform temperature and hence no TCE mismatch occurs.
Thermal cycling is also effective in finding packaging defects such as non-wet solder mounds, solder bumps or C4s and pads with low solder volume for the same reasons.
Applicants have discovered that the labor intensive processes currently used in the microelectronics industry to stress test and burn-in electronic devices can be avoided by exposing the electronic devices to microwave radiation.
Japanese laid-open unexamined patent application No. 63-25966 published Feb. 3, 1988 describes microwave annealing or recrystallization of crystal damage caused by ion implantation of a MISFET channel. There is a reduction in leakage current between the drain region and the channel component after the microwave annealing of the unannealed wafers, which only occurs at temperatures much greater than used in our invention. This patent application refers to a reduction in leakage current of an unannealed wafer which occurs even when the wafers are annealed by conventional means. There is no teaching, suggestion, motivation or incentive to apply microwaves to conventionally annealed wafers to further reduce leakage current.
Japanese laid-open unexamined patent application No. 61-43417 published Mar. 3, 1986, describes using microwaves for crystallization or re-crystallization of a semiconductor surface during the manufacture of a semiconductor device to anneal damage on a wafer surface produced by ion implantation. It is described therein that use of a conventional oven to anneal ion implant damage takes a long time. Moreover, a conventional oven cannot selectively heat only the semiconductor wafer surface to anneal a p-n junction close to the wafer surface. There is no teaching or suggestion of leakage current reduction, device stress test or device burn-in or thermal fatigue cycling.
Japanese laid-open patent application 63-299086 published Dec. 6, 1988 describes an apparatus for applying microwaves to a semiconductor device.
Japanese laid-open patent application 61-32418 published Feb. 15, 1986 is directed to a method of annealing semiconductor wafers using microwaves, such as to anneal crystal damage caused by ion implantation.